The present invention relates to a semiconductor memory device such as a ferroelectric memory.
As a semiconductor memory device, for example, a ferroelectric memory has been known. The ferroelectric memory is of a memory which records binarized data using polarization of each ferroelectric capacitor. As a document that has disclosed the structure and principle of a ferroelectric memory, there is known, for example, a non-patent document 1 (Katsuro Fukamizu, “Low-Power Consumption High-Speed LSI technology”, REALIZE INC., Jan. 31, 1998). As described in the non-patent document 1, one of 1T/1C type and one of 2T/2C type are known as ferroelectric memories.
In the 1T/1C type ferroelectric memory, one memory cell is constituted of a transistor and a ferroelectric capacitor. A stored value is determined or judged by comparing the potential read from the ferroelectric capacitor with a reference potential.
On the other hand, in the 2T/2C type ferroelectric memory, one memory cell is constituted of two transistors and two ferroelectric capacitors. Values “1” and “0” are stored in the two ferroelectric capacitors on a complementary basis. And the stored value is determined by detecting the relationship between the magnitudes of potentials respectively read from the two ferroelectric capacitors.
In the ferroelectric memory, the read potential changes with time when data is stored therein over a long period. FIG. 7 is a graph showing changes in read potential with time. As shown in FIG. 7, a high level V1 of a read potential is lowered and a low level V0 thereof rises with deterioration of a ferroelectric capacitor.
As described above, the 1T/1C type ferroelectric memory compares the read potential V0 or V1 with the reference potential Vref. On the other hand, the 2T/2C type ferroelectric memory compares the read potential V0 and the read potential V1. Thus, the 2T/2C type ferroelectric memory is greater in read margin than the 1T/1C type ferroelectric memory (see FIG. 7).
Thus, the 2T/2C type ferroelectric memory has the advantage that the reliability of stored data over an extended period of time is easy to ensure as compared with the 1T/1C type ferroelectric memory.
On the other hand, the 1T/1C type ferroelectric memory has the merit that since each memory cell is small in circuit scale, high integration is easy. Further, the 1T/1C type ferroelectric memory also has the merit that it is higher or greater in operating speed than the 2T/2C type ferroelectric memory. When, for example, the ferroelectric memory is used as an alternative to a volatile memory such as an SRAM (Static Random Access Memory) (that is, when it is used for temporary storage of data), the reliability of stored data over an extended period of time is not required.
Thus, as the ferroelectric memory, the 2T/2C type is desirable in applications that require long-term reliability. However, there are often cases in which the 1T/1C type is desirable in applications that no require such reliability. Due to such reasons, there has been proposed such a ferroelectric memory as to be usable as the 1T/1C type and the 2T/2C type according to the applications (refer to a patent document 1 (Japanese Unexamined Patent Publication No. Hei 10(1998)-79196)). In the ferroelectric memory disclosed in the patent document 1, the 1T/1C type and the 2T/2C type can be switched by causing a user or vendor to set the potential of each mode signal (refer to, for example, the paragraphs 0042 and 0046 in the same patent document).
In the ferroelectric memory of the patent document 1, however, all memory cells contained in a memory cell block are set to either the 1T/1C type or the 2T/2C type (refer to, for example, the paragraph 0029 in the same patent document). That is, in the ferroelectric memory according to the patent document 1, one memory cell block cannot be used with being divided into a 1T/1C type block and a 2T/2C type block. Besides, the ferroelectric memory of the patent document 1 needs terminals for inputting the mode signals and thereby makes it difficult to perform a reduction in the area of each element.
A ferroelectric memory in which both 1T/1C and 2T/2C types are formed within one chip, has been disclosed in a patent document 2 (Specification of Japanese Patent No. 3592321). The ferroelectric memory of the patent document 2 is provided with 1T/1C type data memory cells and 2T/2C type testing memory cells. However, the ferroelectric memory of the patent document 2 is not capable of switching each data memory cell to the 2T/2C type.